1. Field of the Invention
The present invention relates to the manufacture of semiconductor structures, and more particularly to the reduction of dopant diffusion within regions of a semiconductor substrate.
2. Description of the Related Art
Modern high performance CMOS processes frequently make use of a heavily-doped P-type substrate (a P+ substrate) with a lightly-doped P-type epitaxial layer (a Pxe2x88x92 epitaxial layer) grown upon the substrate. N-wells and P-wells are then formed within the epitaxial layer and P-channel and N-channel transistor structures are then formed within the respective wells. Epitaxial layers are very beneficial for several reasons. They can be grown nearly defect free and typically of much higher quality than the underlying substrate. Moreover, a more heavily-doped substrate may be used with an epitaxial layer because the substrate need never be counter-doped to achieve a region of opposite conductivity type within the substrate. For example, a more heavily-doped P+ substrate may be used with a Pxe2x88x92 epitaxial layer because the substrate need never be counter-doped to achieve an N-type region within the substrate. With an epitaxial layer, the N-type regions are all formed within the more lightly-doped Pxe2x88x92 epitaxial layer, rather than within the underlying P+ substrate. Furthermore, a heavily doped P+ substrate provides a desirable gettering effect for contaminants. Even though substrates with an epitaxial layer may cost twice as much as substrates without such an epitaxial layer, these advantages frequently outweigh the increased cost.
However, the use of such a heavily doped substrate may result in significant upward diffusion of the substrate dopant into the epitaxial layer, where it may affect transistor characteristics. This upward diffusion is particularly problematic with boron-doped P+ substrates, since boron is the most rapidly diffusing species that is used in semiconductor processing. Nevertheless, the same upward diffusion may also be problematic when using heavily-doped N-type substrates (N+ substrates) doped with arsenic or phosphorus. With an epi-substrate, the dopant forming the heavily-doped substrate is subjected to the cumulative heat treatment of the entire process since the epi-substrate constitutes the starting material for the process and the dopant is present within the substrate even for the initial high-temperature processing steps. As a result, the dopant, especially boron, may diffuse significantly toward the surface of the substrate and interfere with desired transistor characteristics.
It is frequently desired to make epitaxial layers as thin as possible. For example, in a process using a P+ substrate with a Pxe2x88x92 epitaxial layer, the transistor structures formed upon such a substrate are desired to be close to the heavily-doped substrate to reduce the N-well, P-well, and substrate parasitic resistances, which consequently improves device performance such as latch-up immunity. But by placing the boron dopant forming the P+ substrate that much closer (vertically) to the transistor structures, the likelihood of boron upward diffusion reaching the transistor regions and causing unwanted effects is magnified.
What is needed is a method for reducing upward diffusion of dopants within the semiconductor substrate, which would allow thinner epitaxial layers to be used with heavily-doped substrates, and more generally allow closer spacing of a heavily-doped layer to overlying transistor structures. A thinner epitaxial layer results in lower parasitic resistances, and hence higher performance transistors, while the reduced upward diffusion lessens the negative interaction with transistor structures formed upon the substrate. Moreover, a thinner epitaxial layer also results in less expensive substrates.
The upward diffusion of dopant within a heavily-doped layer of a semiconductor body, such as a semiconductor substrate, may be retarded by implanting a material to form a barrier layer beneath the top surface of the semiconductor body. The material is implanted to a depth below the structures to be protected, such as source/drain regions of transistor structures formed within the substrate. The implanted material may be either nitrogen or oxygen. In various embodiments, the material may be implanted very early in the process flow, such as after an initial xe2x80x9ccapxe2x80x9d oxide, or alternatively may be implanted at a variety of points in the process flow, including after gate material deposition, gate electrode formation, or source/drain region formation. The implant need not be performed early in the process flow. The barrier layer implant is preferably performed using a high acceleration potential of 1-3 MeV, and results in a barrier layer formed at a depth from 1-5 microns below the top surface.
In one embodiment of the invention, the semiconductor body includes a heavily-doped substrate upon which a lightly-doped epitaxial layer is formed, for example a boron-doped P+ substrate with a Pxe2x88x92 epitaxial layer. In another embodiment, the semiconductor body includes a lightly-doped substrate having an implanted heavily-doped layer separated from the top surface of the semiconductor body. Such an implanted heavily-doped layer affords many of the advantages of using an epitaxial layer on a heavily-doped substrate without the increased cost of growing the epitaxial layer.
The heavily-doped layer may be either N-type, for example using a phosphorus or arsenic dopant, or P-type, for example using a boron dopant. In various embodiments the barrier layer may be formed to reside substantially within the heavily doped layer, to reside partially within the heavily-doped layer and partially between the heavily-doped layer and the top surface, or to reside substantially between the heavily-doped layer and the top surface.
Moreover, in various embodiments the barrier layer implantation may be performed non-selectively which results in an implanted barrier layer which is continuous across the semiconductor body. Alternatively, the barrier layer implantation may be performed selectively into certain regions of the semiconductor body which results in a implanted barrier layer which is discontinuous across the semiconductor body. These certain regions may include a well region of a first conductivity type and exclude well regions of a second conductivity type. For example, the barrier layer implantation may be performed into N-wells but not P-wells.
In one particular embodiment of the present invention, a method for retarding upward diffusion of a dopant within a semiconductor body includes: (1) providing a semiconductor body having a top surface and a heavily-doped layer beneath and separated from the top surface, the heavily-doped layer including a first dopant; (2) forming a transistor gate electrode upon the semiconductor body; (3) forming a transistor source/drain region within the semiconductor body; and (4) implanting a material into the semiconductor body to form a barrier layer of the material beneath and separated from the top surface and at a greater depth than the source/drain region, for retarding the upward diffusion of the first dopant.
In another embodiment of the present invention, a method for retarding upward diffusion of a dopant within a semiconductor body includes: (1) providing a semiconductor body having a top surface and a heavily-doped P+ layer beneath and separated from the top surface, the heavily-doped P+ layer including boron and having an upper boundary; (2) forming a transistor gate electrode upon the semiconductor body; (3) forming a transistor source/drain region within the semiconductor body; and (4) implanting nitrogen into the semiconductor body to form a nitrogen barrier layer beneath and separated from the top surface and at a greater depth than the source/drain region, the barrier layer in close proximity with the upper boundary for retarding the upward diffusion of boron from the heavily-doped P+ layer.
In another embodiment of the present invention, a method of retarding upward diffusion of boron within a semiconductor body includes: (1) providing a semiconductor body having a top surface; (2) forming a transistor gate electrode upon the semiconductor body; (3) forming a transistor source/drain region within the semiconductor body; (4) implanting boron into the semiconductor body to form a heavily-doped P+ layer beneath and separated from the source/drain region; (5) implanting nitrogen into the semiconductor body to form a barrier layer between the heavily-doped P+ layer and the source/drain region, the barrier layer for retarding the upward diffusion of boron forming the heavily-doped P+ layer; and (6) annealing the semiconductor body after both implanting steps.
In one particular embodiment of the present invention, a semiconductor structure includes: (1) a semiconductor body having a top surface and a heavily-doped layer beneath and separated from the top surface, the heavily-doped layer including a first dopant; (2) a transistor gate electrode formed upon the semiconductor body; (3) a transistor source/drain region formed within the semiconductor body; and (4) a barrier layer formed of a material implanted into the semiconductor body beneath and separated from the top surface and at a greater depth than the source/drain region for retarding the upward diffusion of said first dopant.
Other embodiments, features, and advantages of the present invention may be appreciated by careful review of the detailed description below.